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FDMF6730 Driver plus FET Multi-chip Module
August 2008
FDMF6730 Driver plus FET Multi-chip Module
Features
Over 95% efficiency Internal 5V regulator for gate drive 6V-16V input range 1MHz max operating frequency SMOD operation capability for light load efficiency 5A current capability (10A with PASS FET) Current limit set by RDSON sensing to minimize power losses Integrated bootstrap diode
General Description
The FDMF6730 is a high efficiency Driver plus MOSFET power stage solution optimized for Ultra Mobile PC (UMPC) system power voltage supplies. It is fully compliant with the Intel UltraMobile Driver MOS (uDrMOS) Specification. The MOSFETs and driver have been optimized to perform with high efficiency at light and medium loads, ideal for compact PC devices. The internal driver IC integrates two highly efficient LDOs for internal gate-drive and external circuitry. The bootstrap diode is also integrated within the IC. When operating with a single low side MOSFET the uDrMOS module is capable of delivering up to 5A of continuous current. The PASS transistor may be easily routed in parallel with the low side MOSFET to provide up to 10A. The module also incorporates an over current protection flag from an RDSON current sense architecture. The device comes in a 6X6 Power QFN package for improved thermal performance.
Applications
Ultra Mobile PC Notebook Computers
Typical Application
VCC VIN BOOT
VIN
LDO 5V OUT LDO ENABLE LDO OUT
LDO 5V
LDO EN
VSW H
VOUT
LDO OUT
PGND
FDMF6730
LDO ADJ LDRV
PWM CONTROLLER
DRIVE HS
G_PASS
PW M OUT
DRIVE LS CS_O UT CGND D_PASS CS_PROG S_PASS
Figure 1. Power Train Application Circuit
Ordering Information
Part FDMF6730
(c)2008 Fairchild Semiconductor Corporation
Current Rating Max [A] 10
Input Voltage Typical [V] 6-16 1
Frequency Max [KHz] 1000
Device Marking FDMF6730
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FDMF6730 Rev. D2
FDMF6730 Driver plus FET Multi- chip Module
Functional Block Diagram
VC C BO O T PH A SE HD R V
V IN
LDO _5V LDO _EN
5V Reg
V SW H
LD O_O U T
LD O Adjust O CP C urren t T rim m ing
P GN D LD R V G _PASS D _PAS S
LDO_A DJ
D RIVE_HS D RIVE_LS
C G ND
CS _OUT
C S_P RO G
S_PASS
Figure 2. Functional Block Diagram
Pin Configuration
VSWH VSWH VSWH VSWH PGND VIN VIN VIN 10 VIN VIN
1
PGND 40 PGND PGND LDRV VSWH D_PASS G_PASS S_PASS S_PASS S_PASS 31 D (D_PASS) C (CGND) A (VSWH) B (VIN)
11
VIN VIN HDRV VIN CGND PHASE BOOT LDO_5V LDO_OUT
20
LDO_ADJ
30 VCC CGND NC DRIVE_HS D_PASS CS_PROG S_PASS DRIVE_LS CS_OUT
21 LDO_EN
Figure 3. 6mm X 6mm, 40L MLP Bottom View
FDMF6730 Rev. D2
2
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FDMF6730 Driver plus FET Multi- chip Module
Pin Description
Pin
1, 38 - 40 2 - 5, 36, A 6 - 12,14,B 13 15, 24, C 16 17 18 19 20 21 22 23 25 26 27 28, 35, D 29 30-33 34 37
Name
PGND VSWH VIN HDRV CGND PHASE BOOT LDO_5V LDO_OUT LDO_ADJ LDO_EN DRIVE_LS DRIVE_HS VCC CS_OUT CS_PROG D_PASS NC S_PASS G_PASS LDRV
Function
Low Side FET Source Pin. Connect to GND Switch Node Pin. Low Side FET Drain pin. Electrically shorted to PHASE pin Input Voltage Pin. Input voltage for buck converter HDRV pin. High Side driver output. Connected to High Side FET gate pin. IC Ground. Ground return for driver IC. Switch Node Pin for easy bootstrap capacitor routing. Electrically shorted to VSWH pin. Bootstrap Supply Input Pin. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor. 5V Internal LDO Output. Adjustable LDO Output. LDO Adjust Input. Connect to external voltage divider to adjust LDO output. Adjustable LDO Enable Pin. 1 = Enable, 0 = Disable Low Side PWM Input. Connect to PWM controller. High Side PWM Input. Connect to PWM controller. Driver VCC. Connect to 5V. Current Sense Output. 1 = Over-current Fault, 0 = No Fault. Current Sense Program. Pass FET Drain Pin. Connect to VSWH pad for higher output current. No Connect. This pin must be floated. Must not be connected to any pin. Pass FET Source Pin. Connect to PGND pad for higher output current. Pass FET Gate Pin. Connect to LDRV pin for higher output current. LDRV pin. Low Side driver output. Connect to G_PASS pin for higher output current.
Absolute Maximum Rating
Stresses exceeding the absolute maximum rating may damage the device. The device may not function or be operable above the recommended operating conditions and stressing these parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect the device reliability. The absolute maximum rating are stress ratings only.
Parameter
VCC, Drive_LS, Drive_HS, LDO_EN, CS_Prog, CS_Out to GND VIN to PGND BOOT to VSWH VSWH to PGND BOOT to PGND IO(AV) IO(PK) RJPCB PT VIN = 8.4V, VO = 3.3V, fSW = 1MHz, TPCB = 130C VIN = 8.4V, tPULSE = 10 s Junction to PCB Thermal Resistance note 1. TPCB =130 C
Min.
-0.3 -0.3 -0.3 -1.0 -0.3
Max.
6 20 6 27 27 10 35 5.5 3.3
Units
V V V V V A A C/W W C
Operating and Storage Junction Temperature Range
-55
150
Note 1: Package power dissipation based on 4 layer, 2 square inch, 2 oz. copper pad. RJPCB is the steady state junction to PCB thermal resistance with PCB temperature referenced at VSWH pin.
FDMF6730 Rev. D2
3
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FDMF6730 Driver plus FET Multi- chip Module
Recommended Operating Range
The recommended operating conditions table defines the conditions for actual device operation. These conditions are specified to ensure optimal performance to the datasheet specification. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Parameter
VCC VIN VOUT Control Circuit Supply Voltage Output Stage Supply Voltage Output Voltage
Min.
4.5 6 1.5
Typ.
5 8.4 3.3
Max.
5.5 16 5
Units
V V V
Electrical Characteristics
VIN = 8.4V, VCC = 5V, TA = 25C unless otherwise noted.
Parameter
Input Voltage Range Operating Quiescent Current
Symbol
VIN
Conditions
Min.
6
Typ.
Max.
16 2
Units
V mA V
Drive_HS, Drive_LS, LDO_EN Logic Inputs High Level Input Low Level Input Input Current 5V LDO Output Voltage Line Regulation Load Regulation Short Circuit Current Limit Adjustable LDO Adjust Voltage Line Regulation Load Regulation Short Circuit Current Limit Adjust Input Bias Current Over Current Protection CS_Prog Current Thermal Shutdown Threshold Hysteresis Propagation Delay 250ns Timeout tTIMEOUT tDTHH tPDHL tDTLH tPDLL VSWH = 2V, HDRV from HI to LO and LDRV from LO to HI LDRV going LO to VSWH going HI Drive_LS going HI to HDRV going LO VSWH going LO to LDRV going HI Drive_LS going LO to LDRV going LO 250 30 10 20 10 ns ns ns ns ns 150 19
o o
VIH VIL
2.4 0.4 -2 4.7 6V < VIN < 16V 5mA < ILOAD < 100mA 100 5 5 75 180 0.6 3 11 100 180 0.2 30 40 50 0.62 2 5.3
V A V mV mV mA V mV mV mA A A C C
VADJ 6V < VIN < 16V 5mA < ILOAD < 100mA
0.58
FDMF6730 Rev. D2
4
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FDMF6730 Driver plus FET Multi-chip Module
Description of Operation
2-Bit PWM Input
The PWM input is composed of a high side drive and a low side drive input which control the high side and low side FETs respectively. They can also be setup to provide asynchronous rectification (low FET off) and phase shutoff (both FETs off). Truth Table DRIVE_LS 0 0 1 1 DRIVE_HS 0 1 0 1 Low Side MOSFET OFF OFF ON OFF High Side MOSFET OFF ON OFF OFF
Applications Section
Input Capacitor
A High frequency 4.7ceramic X5R must be connected directly from VIN to GND
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor and an external diode. A minimum of 0.1 F high frequency capacitor must be connected between the BOOT and PHASE pin. The PHASE pin is already internally connected to the switch-node.
5V LDO
A minimum of 4.7 F ceramic X5R type must be connected from LDO_5V pin to GND to ensure stable operation and to provide high frequency bypassing for low side driver. This LDO can provide power to the internal logic circuitry and gate drivers via a 10Ohm resistor. A high frequency 1 F ceramic capacitor must be placed from VCC to GND.
One of the most unique features of the uDrMOS is the integrated Pass FET. The pass FET can be easily routed in parallel with the low side FET in order to provide up to 10A of current. When not used as part of the DC-DC controller, it can be used in other applications such as load switching, etc.
PASS FET
Adjustable LDO
A minimum of 10 F ceramic X5R type must be connected close from this pin to GND to insure stable operation for a range of 2.5V to 5V outputs. For output voltages of 0.6V to 2.5V the minimum capacitance must be 22 F ceramic type. A minimum of 1mA load current must be connected from this pin to GND. LDO_ADJ voltage 0.6V typical. LDO_EN: Adjustable LDO enable pin (1= Enable, 0= Disable)
5V LDO
The uDrMOS conveniently incorporates a 5V LDO regulator to drive the internal logic of the IC and gates of the internal MOSFETs.
Adjustable LDO
Another feature of the part is the adjustable 100mA LDO. The LDO output voltage is easily configured with a resistor divider.
Over Current Protection
A resistor connected from the VSWH pin and this pin programs the over current threshold point. CS_OUT is the output of an internal current sense comparator which switches high when the current in low side MOSFET exceeds a pre program level set by the CS_PROG pin. This pin is low during normal operation.
Current Limit
The part also has current limit flag which is set by an internal OCP topology.
FDMF6730 Rev. D2
5
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FDMF6730 Driver plus FET Multi-chip Module
Typical Characteristics
16 14 12 PLOSS, W 10 ILOAD, A 8 6 4 2 0 0 25 50 75
o
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 100 125 150 0
VIN = 8.4V VOUT = 3.3V L = 2.2uH
FSW = 1MHz FSW = 300KHz
VIN = 8.4V VOUT = 3.3V L = 2.2uH FSW = 1MHz
2
4 ILOAD, A
6
8
10
PCB Temperature, C
Figure 4. Safe Operating Area
Figure 5. Power Loss vs. Output Current
1.02 1.00 PLOSS (NORMALIZED) 0.98 0.96 0.94 0.92 0.90 0.88
PLOSS (NORMALIZED)
VIN = 8.4V VOUT = 3.3V ILOAD = 10A L = 2.2uH
1.08 1.06 1.04 1.02 1.00 0.98 0.96
VOUT = 3.3V ILOAD = 10A L = 2.2uH FSW = 1MHz
0.86 300
400
500
600
700
800
900
1000
6
8
10
12
14
16
Switching Frequency, KHz
Input Voltage, V
Figure 6. Power Loss vs. Switching Frequency
Figure 7. Power Loss vs. Input Voltage
1.20 1.15 PLOSS (NORMALIZED) 1.10 1.05 1.00 0.95 0.90 0.85
PLOSS (NORMALIZED)
VIN = 8.4V ILOAD = 10A L = 2.2uH FSW = 1MHz
1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85
VIN = 8.4V VOUT = 3.3V ILOAD = 10A FSW = 1MHz
0.80 1.5
2
2.5
3
3.5
4
4.5
5
1
1.5
2
2.5
3
3.5
Output Voltage, V
Output Inductance, uH
Figure 8. Power Loss vs. Output Voltage
Figure 9. Power Loss vs. Output Inductance
FDMF6730 Rev. D2
6
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FDMF6730 Driver plus FET Multi-chip Module
Typical Characteristics
0.66 0.64 Supply Current, mA Supply Current, mA 4 4.5 5 Driver Supply Voltage, V 5.5 6 0.62 0.60 0.58 0.56 0.54 0.52 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 300
400
500
600
700
800
900
1000
Frequency, kHz
Figure 10. Supply Current vs. Driver Supply
Figure 11. Supply Current vs. Frequency
0.66 LDO_EN Threshold Voltage, V -50 -10 30 70 110 150 0.64 Supply Current, mA 0.62 0.60 0.58 0.56 0.54 0.52 Temperature, oC
1.40 1.38 1.35 1.33 1.30 1.28 1.25 1.23 1.20 -50 -10 30 70 110 150 Temperature, oC
Figure 12. Supply Current vs. Temperature
Figure 13. LDO_EN Threshold Voltage vs. Temperature
1.9 Drive_HS Threshold Voltage, V -50 -10 30 70 110 150 Drive_LS Threshold Voltage, V 1.8 1.7 1.6 1.5 1.4 1.3 1.2 Temperature, oC
1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 -50 -10 30 70 110 150 Temperature, oC
Figure 14. Driver_LS Threshold Voltage vs. Temperature
Figure 15. Driver_HS Threshold Voltage vs. Temperature
FDMF6730 Rev. D2
7
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FDMF6730 Driver plus FET Multi-chip Module
Typical Characteristics
41.0 40.5 CS_Prog Current, uA 40.0 39.5 39.0 38.5 38.0 37.5 -50 -10 30 70 110 150 Temperature, oC
Figure 16. CS_Prog Current vs. Temperature
FDMF6730 Rev. D2
8
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THIS DRAWING IS THE PROPERTY OF FAIRCHILD SEMICONDUCTOR CORPORATION. NO USE THEREOF SHALL BE MADE OTHER THAN AS A REFERENCE FOR PROPOSALS AS SUBMITTED TO FAIRCHILD SEMICONDUCTOR CORPORATION FOR JOBS TO BE EXECUTED IN CONFORMITY WITH SUCH PROPOSALS UNLESS THE CONSENT OF SAID FAIRCHILD SEMICONDUCTOR CORPORATION HAS PREVIOUSLY BEEN OBTAINED. NO PART OF THIS DRAWING SHALL BE COPIED OR DUPLICATED OR ITS CONTENTS DISCLOSED. THE INFORMATION CONTAINED ON THIS DRAWING IS CONFIDENTIAL AND PROPRIETARY.
FDMF6730 Driver plus FET Multi-chip Module
Dimensional Outline and Pad layout
0.10 C
2X
6.00
B A
5.80 4.50
21
31
2.10
0.30
6.00
2.10
11 0.10 C
0.60
1
PIN #1 IDENT
0.80 MAX
TOP VIEW
2X
0.50 TYP 2.10
0.30 2.10
0.35
0.10 C
0.08 C
RECOMMENDED LAND PATTERN
(0.20)
0.05 0.00
SIDE VIEW
(0.20) 2.00? .10 (2X)
C
SEATING PLANE
PIN #1 IDENT
1 11
0.50 40X 0.30
2.00? .10 (2X) (0.20) 4.40? .10 (0.20)
31 40X
0.50
(2.20) 4.40? .10
0.20~0.30
BOTTOM VIEW
0.10 0.05
CAB C
A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION, MO-220. DATED MAY/2005. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. DRAWING FILE NAME: MLP40XREV1
40LD,MLP,QUAD, NON-JEDEC, 6X6 MM, Four DAP
1
9
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FDMF6730 Rev. D2
FDMF6730 Driver plus FET Multi-chip Module
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Rev. I35
FDMF6730 Rev. D2
10
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